View LTC2461IMSPBF_6661906.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

ltc2461/ltc2463 1 24613fa ?50 ?10 10 ?30 50 70 30 90 temperature (c) reference output voltage (v) 1.2520 1.2515 1.2510 1.2505 1.2500 24613 ta01b 1.2480 1.2485 1.2490 1.2495 typical application features applications description ultra-tiny, 16-bit i 2 c ? adcs with 10ppm/c max precision reference the ltc ? 2461/ltc2463 are ultra tiny, 16-bit analog-to- digital converters with an integrated precision reference. they use a single 2.7v to 5.5v supply and communicate through an i 2 c interface. the ltc2461 is single-ended with a 0v to 1.25v input range and the ltc2463 is dif - ferential with a 1.25v input range. both adcs include a 1.25v integrated reference with 2ppm/c drift perfor - mance and 0.1% initial accuracy. the converters are available in a 12-pin 3mm 3mm dfn package or an msop-12 package. they include an integrated oscillator and perform conversions with no latency for multiplexed applications. the ltc2461/ltc2463 include a proprietary input sampling scheme that reduces the average input current several orders of magnitude when compared to conventional delta sigma converters. following a single conversion, the ltc2461/ltc2463 automatically power down the converter and can also be confgured to power down the reference. when both the adc and reference are powered down, the supply current is reduced to 200na. the ltc2461/ltc2463 can sample at 60 conversions per second and, due to the very large oversampling ratio, have extremely relaxed antialiasing requirements. both include continuous internal offset and fullscale calibration algorithms which are transparent to the user, ensuring ac - curacy over time and the operating temperature range. v ref vs temperature n 16-bit resolution, no missing codes n internal reference, high accuracy 10ppm/c (max) n single-ended (ltc2461) or differential (ltc2463) n 2lsb offset error (typ) n 0.01% gain error (typ) n 60 conversions per second n single conversion settling time for multiplexed applications n 1.5ma supply current n 200na sleep current n internal oscillatorno external components required n 2-wire i 2 c interface with two addresses plus one global address for synchronization n ultra-tiny, 12-lead, 3mm 3mm dfn and msop packages n system monitoring n environmental monitoring n direct temperature measurements n instrumentation n data acquisition n embedded adc upgrades l , lt, ltc, ltm, linear technology and the linear logo are registered trademarks of linear technology corporation. all other trademarks are the property of their respective owners. protected by u.s. patents, including 6208279, 6411242, 7088280, 7164378. 10k 10k 10k r scl i 2 c interface sda 0.1f 0.1f 2.7v to 5.5v 10f 0.1f in + refout ref ? v cc 0.1f comp gnd a0 in ? 0.1f ltc2463 24613 ta01a
ltc2461/ltc2463 2 24613fa pin configuration absolute maximum ratings supply voltage (v cc ) ................................... C0.3v to 6v analog input voltage (v in + , v in C , v in , v ref C , v comp , v refout ) ........................... C0.3v to (v cc + 0.3v) digital voltage (v sda , v scl , v a0 ) .......................... C0.3v to (v cc + 0.3v) (notes 1, 2) order information storage temperature range .................. C65c to 150c operating temperature range ltc2461c/ltc2463c ............................... 0c to 70c ltc2461i/ltc2463i ............................. C40c to 85c ltc2463 ltc2463 top view dd package 12-lead (3mm 3mm) plastic dfn 12 13 11 8 9 10 4 5 3 2 1 v cc gnd in ? in + ref ? gnd refout comp a0 gnd scl sda 6 7 t jmax = 125c, ja = 43c/w exposed pad (pin 13) 1 2 3 4 5 6 refout comp a0 gnd scl sda 12 11 10 9 8 7 v cc gnd in ? in + ref ? gnd top view ms package 12-lead plastic msop t jmax = 125c, ja = 135c/w ltc2461 ltc2461 top view dd package 12-lead (3mm 3mm) plastic dfn 12 11 8 9 10 4 5 3 2 1 v cc gnd gnd in ref ? gnd refout comp a0 gnd scl sda 6 7 13 t jmax = 125c, ja = 43c/w exposed pad (pin 13) 1 2 3 4 5 6 refout comp a0 gnd scl sda 12 11 10 9 8 7 v cc gnd gnd in ref ? gnd top view ms package 12-lead plastic msop t jmax = 125c, ja = 135c/w lead free finish tape and reel part marking* package description temperature range ltc2461cdd#pbf ltc2461cdd#trpbf lfgf 12-lead plastic (3mm 3mm) dfn 0c to 70c ltc2461idd#pbf ltc2461idd#trpbf lfgf 12-lead plastic (3mm 3mm) dfn C40c to 85c ltc2461cms#pbf ltc2461cms#trpbf 2461 12-lead plastic msop 0c to 70c ltc2461ims#pbf ltc2461ims#trpbf 2461 12-lead plastic msop C40c to 85c ltc2463cdd#pbf ltc2463cdd#trpbf lfgg 12-lead plastic (3mm 3mm) dfn 0c to 70c ltc2463idd#pbf ltc2463idd#trpbf lfgg 12-lead plastic (3mm 3mm) dfn C40c to 85c ltc2463cms#pbf ltc2463cms#trpbf 2463 12-lead plastic msop 0c to 70c ltc2463ims#pbf ltc2463ims#trpbf 2463 12-lead plastic msop C40c to 85c consult ltc marketing for parts specifed with wider operating temperature ranges. *the temperature grade is identifed by a label on the shipping container. consult ltc marketing for information on non-standard lead based fnish parts. for more information on lead free part marking, go to: http://www.linear.com/leadfree/ for more information on tape and reel specifcations, go to: http://www.linear.com/tapeandreel/
ltc2461/ltc2463 3 24613fa electrical characteristics parameter conditions min typ max units resolution (no missing codes) (note 3) l 16 bits integral nonlinearity (note 4) l 1 8 lsb offset error ltc2461, 30hz, ltc2463 ltc2461, 60hz l 2 5 15 lsb lsb offset error drift 0.02 lsb/c gain error includes contributions of adc and internal reference l 0.01 0.25 % of fs gain error drift includes contributions of adc and internal reference c-grade i-grade l 2 5 10 ppm/c ppm/c transition noise 2.2 v rms power supply rejection dc 80 db the l denotes the specifcations which apply over the full operating temperature range, otherwise specifcations are at t a = 25c. (note 2) analog inputs the l denotes the specifcations which apply over the full operating temperature range, otherwise specifcations are at t a = 25c. symbol parameter conditions min typ max units v cc supply voltage l 2.7 5.5 v i cc supply current conversion nap sleep l l l 1.5 800 0.2 2.5 1500 2 ma a a the l denotes the specifcations which apply over the full operating temperature range, otherwise specifcations are at t a = 25c. symbol parameter conditions min typ max units v in + positive input voltage range ltc2463 l 0 v ref v v in C negative input voltage range ltc2463 l 0 v ref v v in input voltage range ltc2461 l 0 v ref v v or + , v ur + overrange/underrange voltage, in + v in C = 0.625v (see figure 3) 8 lsb v or C , v ur C overrange/underrange voltage, inC v in + = 0.625v (see figure 3) 8 lsb c in in + , in C , in sampling capacitance 0.35 pf i dc_leak(in + , in C , in) in + , in C dc leakage current (ltc2463) in dc leakage current (ltc2461) v in = gnd or v cc (note 8) v in = gnd or v cc (note 8) l l C10 C10 1 1 10 10 na na i conv input sampling current (note 5) 50 na v ref refout output voltage l 1.247 1.25 1.253 v refout voltage temperature coeffcient (note 9) c-grade i-grade l 2 5 10 ppm/c ppm/c reference line regulation 2.7v v cc 5.5v C90 db reference short circuit current v cc = 5.5, forcing refout to gnd l 35 ma comp pin short circuit current v cc = 5.5, forcing refout to gnd l 200 a reference load regulation 2.7v v cc 5.5v, i out = 100a sourcing 3.5 mv/ma reference output noise density c comp = 0.1f, c refout = 0.1f, at f = 1khz 30 nv/ hz power requirements
ltc2461/ltc2463 4 24613fa the l denotes the specifcations which apply over the full operating temperature range, otherwise specifcations are at t a = 25c. (notes 2, 7) symbol parameter conditions min typ max units v ih high level input voltage l 0.7v cc v v il low level input voltage l 0.3v cc v i i digital input current l C10 10 a v hys hysteresis of schmidt trigger inputs (note 3) l 0.05v cc v v ol low level output voltage (sda) i = 3ma l 0.4 v i in input leakage 0.1v cc v in 0.9v cc l 1 a c i capacitance for each i/o pin l 10 pf c b capacitance load for each bus line l 400 pf v ih(a0) high level input voltage for address pin l 0.95v cc v v il(a0) low level input voltage for address pin l 0.05v cc v i 2 c inputs and outputs the l denotes the specifcations which apply over the full operating temperature range, otherwise specifcations are at t a = 25c. (notes 2, 7) symbol parameter conditions min typ max units t conv conversion time l 13 16.6 23 ms f scl scl clock frequency l 0 400 khz t hd(sda,sta) hold time (repeated) start condition l 0.6 ms t low low period of the scl pin l 1.3 ms t high high period of the scl pin l 0.6 ms t su(sta) set-up time for a repeated start condition l 0.6 ms t hd(dat) data hold time l 0 0.9 ms t su(dat) data set-up time l 100 ns t r rise time for sda, scl signals (note 6) l 20 + 0.1c b 300 ns t f fall time for sda, scl signals (note 6) l 20 + 0.1c b 300 ns t su(sto) set-up time for stop condition l 0.6 ms t buf bus free time between a stop and start condition l 1.3 ms t of output fall time v ihmin to v ilmax bus load c b = 10pf to 400pf (note 6) l 20 + 0.1c b 250 ns t sp input spike suppression l 50 ns i 2 c timing characteristics note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. note 2: all voltage values are with respect to gnd. v cc = 2.7v to 5.5v unless otherwise specifed. note 3: guaranteed by design, not subject to test. note 4: integral nonlinearity is defned as the deviation of a code from a straight line passing through the actual endpoints of the transfer curve. guaranteed by design and test correlation. note 5: input sampling current is the average input current drawn from the input sampling network while the ltc2461/ltc2463 are converting. note 6: c b = capacitance of one bus line in pf. note 7: all values refer to v ih(min ) and v il(max) levels. note 8: a positive current is fowing into the dut pin. note 9: voltage temperature coeffcient is calculated by dividing the maximum change in output voltage by the specifed temperature range.
ltc2461/ltc2463 5 24613fa typical performance characteristics offset error vs temperature adc gain error vs temperature transition noise vs temperature conversion mode power supply current vs temperature sleep mode power supply current vs temperature v ref vs temperature (t a = 25c, unless otherwise noted) temperature (c) offset error (lsb) 1 5 24613 g04 ?1 0 2 3 4 ?2 ?3 ?4 ?5 v cc = 5.5v v cc = 4.1v v cc = 2.7v ?50 ?10 10 ?30 50 70 30 90 temperature (c) ?50 adc gain error (lsb) 25 5 24613 g05 0 15 10 20 ?25 25 50 75 0 100 v cc = 5.5v v cc = 4.1v v cc = 2.7v temperature (c) transition noise rms (v) 6 10 24613 g06 4 5 7 8 9 3 2 1 0 ?50 ?10 10 ?30 50 70 30 90 v cc = 5.5v v cc = 2.7v ?50 ?10 10 ?30 50 70 30 90 v cc = 5.5v v cc = 2.7v temperature (c) conversion current (ma) 2.0 1.9 24613 g07 1.4 1.5 1.6 1.7 1.8 1.3 1.2 1.1 1.0 v cc = 4.1v ?50 ?10 10 ?30 50 70 30 90 v cc = 5.5v v cc = 2.7v v cc = 4.1v temperature (c) sleep current (na) 350 24613 g08 150 300 250 200 100 50 0 ?50 ?10 10 ?30 50 70 30 90 temperature (c) reference output voltage (v) 1.2508 24613 g09 1.2502 1.2503 1.2504 1.2505 1.2506 1.2507 v cc = 5v integral nonlinearity (v cc = 5.5v) integral nonlinearity (v cc = 2.7v) inl vs temperature differential input voltage (v) ?1.25 ?0.75 ?0.25 inl (lsb) 1 3 24613 g02 ?1 0 2 ?2 ?3 0.25 0.75 1.25 t a = ?45c, 25c, 90c temperature (c) ?55 inl (lsb) 1 3 24613 g03 ?1 0 2 ?2 ?3 ?35 ?15 25 45 65 85 5 125105 v cc = 5.5v, 4.1v, 2.7v differential input voltage (v) ?1.25 ?0.75 ?0.25 inl (lsb) 1 3 24613 g01 ?1 0 2 ?2 ?3 0.25 0.75 1.25 t a = ?45c, 25c, 90c
ltc2461/ltc2463 6 24613fa pin functions refout (pin 1): reference output pin. nominally 1.25v, this voltage sets the fullscale input range of the adc. for noise and reference stability connect to a 0.1f capacitor tied to gnd. this capacitor value must be less than or equal to the capacitor tied to the reference compensation pin (comp). refout cannot be overdriven by an external reference. for applications that require an input range greater than 0v to 1.25v, please refer to the ltc2451/ ltc2453. comp (pin 2): internal reference compensation pin. for low noise and reference stability, tie a 0.1f capacitor to gnd. a0 (pin 3): chip address control pin. the a0 pin can be tied to gnd or v cc . if a0 is tied to gnd, the ltc2461/ ltc2463 i 2 c address is 0010100. if a0 is tied to v cc , the ltc2461/ltc2463 i 2 c address is 1010100. gnd (pins 4, 7, 11): ground. connect directly to the ground plane through a low impedance connection. scl (pin 5): serial clock input of the i 2 c interface. the ltc2461/ltc2463 can only act as a slave and the scl pin only accepts external serial clock. data is shifted into the sda pin on the rising edges of scl and output through the sda pin on the falling edges of scl. sda (pin 6): bidirectional serial data line of the i 2 c inter - face. the conversion result is output through the sda pin. the pin is high impedance unless the ltc2461/ltc2463 is in the data output mode. while the ltc2461/ltc2463 is in the data output mode, sda is an open drain pull down (which requires an external 1.7k pull-up resistor to v cc ). ref C (pin 8): negative reference input to the adc. the voltage on this pin sets the zero input to the adc. this pin should tie directly to ground or the ground sense of the input sensor. in + (ltc2463), in (ltc2461) (pin 9): positive input volt- age for the ltc2463 differential device. adc input for the ltc2461 single-ended device. in C (ltc2463), gnd (ltc2461) (pin 10): negative input voltage for the ltc2463 differential device. gnd for the ltc2461 single-ended device. v cc (pin 12): positive supply voltage. bypass to gnd with a 10f capacitor in parallel with a low-series-inductance 0.1f capacitor located as close to pin 12 as possible. exposed pad (pin 13 C dfn package): ground. connect directly to the ground plane through a low impedance connection. typical performance characteristics (t a = 25c, unless otherwise noted) power supply rejection vs frequency at v cc conversion time vs temperature frequency at v cc (hz) 1 rejection (db) 0 24613 g10 ?20 ?40 ?60 ?80 ?100 ?120 10 1k 10k 100k 1m 100 10m t a = 25c v cc = 4.1v temperature (c) ?50 conversion time (ms) 21 24613 g11 20 16 17 18 19 15 14 ?25 25 50 75 0 100 v cc = 5v, 4.1v, 3v v ref vs v cc 2.0 3.5 2.5 4.0 3.0 5.0 5.5 4.5 6.0 v cc (v) v ref (v) 1.24892 1.24891 24613 g12 1.24884 1.24885 1.24886 1.24887 1.24888 1.24889 1.24890 t a = 25c
ltc2461/ltc2463 7 24613fa applications information converter operation converter operation cycle the ltc2461/ltc2463 are low power, delta sigma, ana - log to digital converters with a simple i 2 c interface (see figure 1). the ltc2463 has a fully differential input while the ltc2461 is single-ended. both are pin and software compatible. their operation is composed of three distinct states: convert, sleep/nap, and data input/output (see figure 2). the operation begins with the convert state. once the conversion is fnished, the converter auto- matically powers down (nap) or, under user control, both the converter and reference are powered down (sleep). the conversion result is held in a static register while the device is in this state. the cycle concludes with the data input/output state. once all 16-bits are read the device begins a new conversion. the convert state duration is determined by the ltc2461/ ltc2463 conversion time (nominally 16.6 milliseconds). once started, this operation can not be aborted except by a low power supply condition (v cc < 2.1v) which generates an internal power-on reset signal. after the completion of a conversion, the ltc2461/ltc2463 enters the sleep/nap state and remains there until a valid figure 2. ltc2461/ltc2463 state transition diagram read/write is acknowledged. following this condition, the adc transitions into the data input/output state. while in the sleep/nap state, the ltc2461/ltc2463s converters are powered down. this reduces the supply data input/output sleep/nap convert power-on reset yes 24613 f02 stop or read 16 bits read/write acknowledge no yes no block diagram figure 1. functional block diagram ? a/d converter decimating sinc filter sda refout comp ref ? in + (in) in ? (gnd) scl a0 24613 bd ? ? a/d converter internal reference ( ) parenthesis indicate ltc2461 i 2 c interface internal oscillator 1 v cc 12 2 3 5 6 8 gnd 4, 7, 11, 13 (dd package) 9 10
ltc2461/ltc2463 8 24613fa applications information current by approximately 50%. while in the nap state, the reference remains powered up. to power down the reference in addition to the converter, the user can select the sleep mode during the data input/output state. once the next conversion is complete, sleep state is entered and power is reduced to 200na. the reference is powered up once a valid read/write is acknowledged. the reference startup time is 12ms (if the reference and compensation capacitor values are both 0.1f). power-up sequence when the power supply voltage (v cc ) applied to the con - verter is below approximately 2.1v, the adc performs a power-on reset. this feature guarantees the integrity of the conversion result. when v cc rises above this critical threshold, the converter generates an internal power-on reset (por) signal for approximately 0.5ms. the por signal clears all internal registers. following the por signal, the ltc2461/ltc2463 start a conversion cycle and follow the succession of states shown in figure 2. the reference startup time following a por is 12ms (c comp = c refout = 0.1f). the frst conver - sion following power-up will be invalid since the reference voltage has not completely settled. the frst conversion following power up can be discarded using the data abort command or simply read and ignored. the following con- versions are accurate to the device specifcations. ease of use the ltc2461/ltc2463 data output has no latency, flter settling delay or redundant results associated with the conversion cycle. there is a one-to-one correspondence between the conversion and the output data. therefore, multiplexing multiple analog input voltages requires no special actions. the ltc2461/ltc2463 perform offset calibrations every conversion cycle. this calibration is transparent to the user and has no effect upon the cyclic operation described previously. the advantage of continuous calibration is stability of the adc performance with respect to time and temperature. the ltc2461/ltc2463 include a proprietary input sampling scheme that reduces the average input current by several orders of magnitude when compared to traditional delta- sigma architectures. this allows external flter networks to interface directly to the ltc2461/ltc2463. since the average input sampling current is 50na, an external rc lowpass flter using 1k and 0.1f results in <1lsb additional error. additionally, there is negligible leakage current between in + and in C . input voltage range (ltc2461) ignoring offset and full-scale errors, the ltc2461 will theoretically output an all zero digital result when the input is at ground (a zero scale input) and an all one digital result when the input is at v ref (v refout = 1.25v). in an underrange condition, for all input voltages below zero scale, the converter will generate the output code 0. in an overrange condition, for all input voltages greater than v ref , the converter will generate the output code 65535. for applications that require an input range greater than 0v to 1.25v, please refer to the ltc2451. input voltage range (ltc2463) as mentioned in the output data format section, the output code is given as 32768 ? (v in + C v in C )/v ref + 32768. for (v in + C v in C ) v ref , the output code is clamped at 65535 (all ones). for (v in + C v in C ) Cv ref , the output code is clamped at 0 (all zeroes). the ltc2463 includes a proprietary architecture that can, typically, digitize each input up to 8 lsbs above
ltc2461/ltc2463 9 24613fa v ref and below gnd, if the differential input is within v ref . as an example (figure 3), if the user desires to measure a signal slightly below ground, the user could set v in C = gnd. if v in + = gnd, the output code would be approximately 32768. if v in + = gnd C 8lsb = C0.305mv, the output code would be approximately 32760. for ap- plications that require an input range greater than 1.25v, please refer to the ltc2453. the data line is free, it is high. data on the i 2 c bus can be transferred at rates up to 100kbits/s in the standard-mode and up to 400kbits/s in the fast-mode. upon entering the data input/output state, sda outputs the sign (d15) of the conversion result. during this state, the adc shifts the conversion result serially through the sda output pin under the control of the scl input pin. there is no latency in generating this data and the result corresponds to the last completed conversion. a new bit of data appears at the sda pin following each falling edge detected at the scl input pin and appears from msb to lsb. the user can reliably latch this data on every rising edge of the external serial clock signal driving the scl pin. each device on the i 2 c bus is recognized by a unique address stored in that device and can operate either as a transmitter or receiver, depending on the function of the device. in addition to transmitters and receivers, devices can also be considered as masters or slaves when performing data transfers. a master is the device which initiates a data transfer on the bus and generates the clock signals to permit that transfer. devices addressed by the master are considered a slave. the address of the ltc2461/ltc2463 is 0010100 (if a0 is tied to gnd) or 1010100 (if a0 is tied to v cc ). the ltc2461/ltc2463 can only be addressed as a slave. it can only transmit the last conversion result. the serial clock line, scl, is always an input to the ltc2461/ltc2463 and the serial data line sda is bidirectional. figure 4 shows the defnition of the i 2 c timing. applications information figure 4. defnition of timing for fast/standard mode devices on the i 2 c bus sda scl s sr p s t hd(sta) t hd(dat) t su(sta) t su(sto) t su(dat) t low t hd(sda) t sp t buf t r t f t r t f t high 24613 f04 figure 3. output code vs v in + with v in C = 0 (ltc2463) v in + /v ref + ?0.001 output code 4 12 20 0.001 24613 f03 ?4 ?12 0 8 16 ?8 ?16 ?20 ?0.005 0 0.005 0.0015 signals below gnd i 2 c interface the ltc2461/ltc2463 communicate through an i 2 c in- terface. the i 2 c interface is a 2-wire open-drain interface supporting multiple devices and masters on a single bus. the connected devices can only pull the data line (sda) low and can never drive it high. sda must be externally connected to the supply through a pull-up resistor. when
ltc2461/ltc2463 10 24613fa applications information the start and stop conditions a start (s) condition is generated by transitioning sda from high to low while scl is high. the bus is consid - ered to be busy after the start condition. when the data transfer is fnished, a stop (p) condition is generated by transitioning sda from low to high while scl is high. the bus is free after a stop is generated. start and stop conditions are always generated by the master. when the bus is in use, it stays busy if a repeated start (sr) is generated instead of a stop condition. the repeated start timing is functionally identical to the start and is used for reading from the device before the initiation of a new conversion. data transferring after the start condition, the i 2 c bus is busy and data transfer can begin between the master and the addressed slave. data is transferred over the bus in groups of nine bits, one byte followed by one acknowledge (ack) bit. the master releases the sda line during the ninth scl clock cycle. the slave device can issue an ack by pulling sda low or issue a not acknowledge (nak) by leaving the sda line high impedance (the external pull-up resistor will hold the line high). change of data only occurs while the clock line (scl) is low. output data format after a start condition, the master sends a 7-bit address followed by a read request (r) bit. the bit r is 1 for a read request. if the 7-bit address matches the ltc2461/ ltc2463 s address (0010100 or 1010100, depending on the state of the pin a0) the adc is selected. when the device is addressed during the conversion state, it does not accept the request and issues a nak by leaving the sda line high. if the conversion is complete, the ltc2461/ltc2463 issue an ack by pulling the sda line low . following the ack, the ltc2461/ltc2463 can output data. the data output stream is 16 bits long and is shifted out on the falling edges of scl (see figure 5a). the data input/output state is concluded once all 16 data bits have been read or after a stop condition. the ltc2463 (differential input) output code is given by 32768 ? (v in + C v in C )/v ref + 32768. the frst bit output by the ltc2463, d15, is the msb, which is 1 for v in + v in C and 0 for v in + < v in C . this bit is followed by succes - sively less signifcant bits (d14, d13, ) until the lsb is output by the ltc2463, see table 1. the ltc2461 (single-ended input) output code is a direct binary encoded result, see table 1. 1 7 8 9 2 3 1 8 d8 d13d14 msb d15 r sda scl 7-bit address start by master d7 d6 d5 d0 lsb 9 1 2 3 8 9 ack by master nack by master sleep data output conversion 24613 f05a ack by ltc2461/ltc2463 figure 5a. read sequence timing diagram
ltc2461/ltc2463 11 24613fa applications information data input format after a start condition, the master sends a 7-bit ad - dress followed by a read/write request (r/ w ) bit. the r/w bit is 0 for a write. the data input word is 4 bits long and consists of two enable bits (en1 and en2) and two programming bits (spd and slp), see figure 5b. en1 is applied to the frst rising edge of scl after a valid write address is acknowledged. programming is enabled by setting en1 = 1 and en2 = 0. the speed bit (spd) is only used by the ltc2461. in the default mode, spd = 0, the output rate is 60hz and con - tinuous background offset calibration is not performed. by changing the spd bit to 1, background offset calibration is performed and the output rate is reduced to 30hz. the ltc2463 data output rate is always 60hz and background offset calibration is performed (spd = dont care). the sleep bit (slp) is used to power down the on chip reference. in the default mode, the reference remains powered up even when the adc is powered down. if the slp bit is set high, the reference will power down after the next conversion is complete. it will remain powered down until a valid address is acknowledged. the reference startup time is approximately 12ms. in order to ensure a stable reference for the following conversions, either the data input/output time should be delayed 12ms after an address acknowledge or the frst conversion following a reference start up should be discarded. figure 5b. timing diagram for writing to the ltc2461/ltc2463 sda scl en1 en2 spd slp w sleep start by master data input 7 8 9 1 2 3 4 5 6 7 8 9 1 2 ? 7-bit address ack by ltc2461/ltc2463 ack by ltc2461/ltc2463 24613 f03 table 1. ltc2461/ltc2463 output data format single ended input v in (ltc2461) differential input voltage v in + C v in C (ltc2463) d15 (msb) d14 d13 d12...d2 d1 d0 (lsb) corresponding decimal value v ref v ref 1 1 1 1 1 1 65535 v ref C 1lsb v ref C 1lsb 1 1 1 1 1 0 65534 0.75 ? v ref 0.5 ? v ref 1 1 0 0 0 0 49152 0.75 ? v ref C 1lsb 0.5 ? v ref C 1lsb 1 0 1 1 1 1 49151 0.5 ? v ref 0 1 0 0 0 0 0 32768 0.5 ? v ref C 1lsb C1lsb 0 1 1 1 1 1 32767 0.25 ? v ref C0.5 ? v ref 0 1 0 0 0 0 16384 0.25 ? v ref C 1lsb C0.5 ? v ref C 1lsb 0 0 1 1 1 1 16383 0 Cv ref 0 0 0 0 0 0 0
ltc2461/ltc2463 12 24613fa figure 7b. start a new conversion without reading old conversion result figure 7c. synchronize the ltc2461/ltc2463 with the global address call sleep s p r ack read (optional) data output conversion conversion 24613 f07a 7-bit address (0010100 or 1010100) applications information figure 6. consecutive reading sleep sleep s p r ack read read data output conversion conversion 24613 f06 s r p ack conversion data output 7-bit address (0010100 or 1010100) 7-bit address (0010100 or 1010100) operation sequence continuous read conversions from the ltc2461/ltc2463 can be continu - ously read, see figure 6. the r/ w is 1 for a read. at the end of a read operation, a new conversion automatically begins. at the conclusion of the conversion cycle, the next result may be read using the method described above. if the conversion cycle is not complete and a valid address selects the device, the ltc2461/ltc2463 generate a nak signal indicating the conversion cycle is in progress. see figure 7a for an example state diagram. discarding a conversion result and initiating a new conversion it is possible to start a new conversion without reading the old result, as shown in figure 7b. following a valid 7-bit address, a read request (r/w) bit, and a valid ack, a stop command will start a new conversion. synchronizing the ltc2461/ltc2463 with the global address call the ltc2461/ltc2463 can also be synchronized with the global address call (see figure 7c). to achieve this, the ltc2461/ltc2463 must frst have completed the figure 7a. i 2 c state diagram 24613 f07b 7-bit address: 0010100 or 1010100 write input configuration (figure 5b) for cycle n i 2 c start r/w bit low write input configuration (figure 5b) i 2 c stop convert conversion finished ack ack ack nak i 2 c (repeat) start r/w bit low 7-bit address: 0010100 or 1010100 i 2 c start r/w bit high read data from cycle n-1 i 2 c stop convert conversion finished 7-bit address: 0010100 or 1010100 global address (1110111) sleep conversion s w ack write (optional) p 24613 f07c data input
ltc2461/ltc2463 13 24613fa applications information conversion cycle. the master issues a start, followed by the ltc2461/ltc2463 global address 1110111, and a write request. the ltc2461/ltc2463 will be selected and acknowledge the request. if desired, the master then sends the write byte to program the 30hz or 60hz mode. after the optional write byte, the master ends the write operation with a stop. this will update the confguration registers (if a write byte was sent) and initiate a new conversion on the ltc2461/ltc2463, as shown in figure?7c. in order to synchronize the start of the conversion without affecting the confguration registers, the write operation can be aborted with a stop. this initiates a new conversion on the ltc2461/ltc2463 without changing the confgura - tion registers. preserving the converter accuracy the ltc2461/ltc2463 are designed to minimize the conver - sion results sensitivity to device decoupling, pcb layout, antialiasing circuits, line and frequency perturbations. nev - ertheless, in order to preserve the high accuracy capability of this part, some simple precautions are desirable. digital signal levels due to the nature of cmos logic, it is advisable to keep input digital signals near gnd or v cc . voltages in the range of 0.5v to v cc C 0.5v may result in additional current leakage from the part. undershoot and overshoot should also be minimized, particularly while the chip is convert - ing. excessive noise on the digital lines could degrade the adc performance. driving v cc and gnd in relation to the v cc and gnd pins, the ltc2461/ltc2463 combines internal high frequency decoupling with damping elements, which reduce the adc performance sensitivity to pcb layout and external components. nevertheless, the very high accuracy of this converter is best pre - served by careful low and high frequency power supply decoupling. a 0.1f, high quality, ceramic capacitor in parallel with a 10f low esr ceramic capacitor should be connected between the v cc and gnd pins, as close as possible to the package. the 0.1f capacitor should be placed closest to the adc package. it is also desirable to avoid any via in the circuit path, starting from the converter v cc pin, passing through these two decoupling capacitors, and returning to the converter gnd pin. the area encompassed by this circuit path, as well as the path length, should be minimized. as shown in figure 8, ref C is used as the negative refer - ence voltage input to the adc. this pin can be tied directly to ground or kelvined to sensor ground. in the case where ref C is used as a sense input, it should be bypassed to ground with a 0.1f ceramic capacitor in parallel with a 10f low esr ceramic capacitor. very low impedance ground and power planes, and star connections at both v cc and gnd pins, are preferable. the v cc pin should have two distinct connections: the frst to the decoupling capacitors described above, and the second to the ground return for the power supply voltage source. figure 8. ltc2461/ltc2463 analog input/reference equivalent circuit r sw 15k (typ) i leak i leak v cc v cc v cc v cc c eq 0.35pf (typ) in + in ? ref ? refout internal reference 24613 f08 r sw 15k (typ) i leak i leak r sw 15k (typ) i leak i leak r sw 15k (typ) i leak i leak
ltc2461/ltc2463 14 24613fa applications information refout and comp the on-chip 1.25v precision reference is internally tied to the ltc2461/ltc2463 converters reference input and its output to the refout pin. a 0.1f capacitor should be placed on the refout pin. it is possible to reduce this capacitor, but the transition noise increases. a 0.1f capacitor should also be placed on the comp pin. this pin is tied to an internal point in the reference and is used for stability. in order for the reference to remain stable the capacitor placed on the comp pin must be greater than or equal to the capacitor tied to the refout pin. the refout pin should not be overridden by an external voltage. if a reference voltage greater than 1.25v is required, the ltc2451/ltc2453 should be used. the internal reference has a corresponding start up time depending on the size of the capacitors tied to the refout and comp pins. this start up time is typically 12ms when 0.1f capacitors are used. at initial power up, the frst conversion result can be aborted or ignored. at the completion of this frst conversion, the reference has settled and all subsequent conversions are valid. if the reference is put to sleep (program slp = 1) the refer - ence is powered down after the next conversion. this last conversion result is valid. on a valid address acknowledge, the reference is powered back up. in order to ensure the reference output has settled before the next conversion, the power up time can be extended by delaying the data read 12ms. once all 16 bits are read from the device, the next conversion automatically begins. in the default opera - tion, the reference remains powered up at the conclusion of the conversion cycle. driving v in + and v in C the input drive requirements can best be analyzed using the equivalent circuit of figure 9. the input signal v sig is connected to the adc input pins (in + and in C ) through an equivalent source resistance r s . this resistor includes both the actual generator source resistance and any additional optional resistors connected to the input pins. optional input capacitors c in are also connected to the adc input pins. this capacitor is placed in parallel with the input parasitic capacitance c par . this parasitic capacitance figure 9. ltc2461/ltc2463 input drive equivalent circuit i leak i leak r sw 15k (typ) i conv c in in + (ltc2463) in (ltc2461) v cc v sig + v sig ? r s c eq 0.35pf (typ) c par + ? 24613 f09 i leak i leak r sw 15k (typ) i conv c in in ? (ltc2463) v cc r s c eq 0.35pf (typ) c par + ? includes elements from the printed circuit board (pcb) and the associated input pin of the adc. depending on the pcb layout, c par has typical values between 2pf and 15pf. in addition, the equivalent circuit of figure 9 includes the converter equivalent internal resistor r sw and sampling capacitor c eq . there are some immediate trade-offs in r s and c in without needing a full circuit analysis. increasing r s and c in can give the following benefts: 1) due to the ltc2461/ltc2463 s input sampling algo - rithm, the input current drawn by in + , in C or in over a conversion cycle is typically 50na. a high r s ? c in attenuates the high frequency components of the input current, and r s values up to 1k result in <1lsb error. 2) the bandwidth from v sig is reduced at the input pins (in + , in C or in). this bandwidth reduction isolates the adc from high frequency signals, and as such provides simple antialiasing and input noise reduction. 3) switching transients generated by the adc are attenu - ated before they go back to the signal source. 4) a large c in gives a better ac ground at the input pins, helping reduce refections back to the signal source. 5) increasing r s protects the adc by limiting the current during an outside-the-rails fault condition. there is a limit to how large r s ? c in should be for a given application. increasing r s beyond a given point increases the voltage drop across r s due to the input current,
ltc2461/ltc2463 15 24613fa applications information to the point that signifcant measurement errors exist. additionally, for some applications, increasing the r s ? c in product too much may unacceptably attenuate the signal at frequencies of interest. for most applications, it is desirable to implement c in as a high-quality 0.1f ceramic capacitor and to set r s 1k. this capacitor should be located as close as possible to the actual in + , in C or in package pin. furthermore, the area encompassed by this circuit path, as well as the path length, should be minimized. in the case of a 2-wire sensor that is not remotely grounded, it is desirable to split r s and place series resistors in the adc input line as well as in the sensor ground return line, which should be tied to the adc gnd pin using a star connection topology. figure 10 shows the measured ltc2463 inl vs input voltage as a function of r s value with an input capacitor c in = 0.1f. in some cases, r s can be increased above these guidelines. the input current is zero when the adc is either in sleep or i/o modes. thus, if the time constant of the input rc circuit t = r s ? c in , is of the same order of magnitude or longer than the time periods between actual conversions, then one can consider the input current to be reduced correspondingly. these considerations need to be balanced out by the input signal bandwidth. the 3db bandwidth 1/(2pr s c in ). finally, if the recommended choice for c in is unacceptable for the users specifc application, an alternate strategy is to eliminate c in and minimize c par and r s . in practical terms, this confguration corresponds to a low impedance sensor directly connected to the adc through minimum length traces. actual applications include current measurements through low value sense resistors, temperature measure - ments, low impedance voltage source monitoring, and so on. the resultant inl vs v in is shown in figure 11. the measurements of figure 11 include a capacitor c par cor - responding to a minimum sized layout pad and a minimum width input trace of about 1 inch length. signal bandwidth, transition noise and noise equivalent input bandwidth the ltc2461/ltc2463 include a sinc 1 type digital flter with the frst notch located at f 0 = 60hz. as such, the 3db input signal bandwidth is 26.54hz. the calculated ltc2461/ltc2463 input signal attenuation vs frequency over a wide frequency range is shown in figure 12. the calculated ltc2461/ltc2463 input signal attenuation vs frequency at low frequencies is shown in figure 13. the converter noise level is about 2.2v rms and can be mod- eled by a white noise source connected at the input of a noise-free converter. on a related note, the ltc2463 uses two separate a/d converters to digitize the positive and negative inputs. each of these a/d converters has 2.2v rms transition noise. if one of the input voltages is within this small transition noise band, then the output will fuctuate one bit, regardless of the value of the other input voltage. if both of the input voltages are within their transition noise bands, the output can fuctuate 2 bits. for a simple system noise analysis, the v in drive circuit can be modeled as a single-pole equivalent circuit character - ized by a pole location f i and a noise spectral density n i . if the converter has an unlimited bandwidth, or at least a bandwidth substantially larger than f i , then the total noise contribution of the external drive circuit would be: v n = n i p / 2 ? f i then, the total system noise level can be estimated as the square root of the sum of (v n 2 ) and the square of the ltc2461/ltc2463 noise foor (~2.2v 2 ).
ltc2461/ltc2463 16 24613fa figure 12. ltc2463 input signal attentuation vs frequency figure 13. ltc2463 input signal attenuation vs frequency (low frequencies) applications information input signal frequency (mhz) 0 input signal attenuation (db) ?40 0 1.00 1.25 1.50 24613 f12 ?60 ?80 ?20 ?100 2.5 5.0 7.5 v cc = 5v t a = 25c input signal frequency (hz) 0 input signal attenuatioin (db) ?20 ?10 0 480 24613 f13 ?30 ?40 ?25 ?15 ?5 ?35 ?45 ?50 12060 240180 360 420 540 300 600 v cc = 5v t a = 25c figure 10. measured inl vs input voltage (c in = 0.1f) figure 11. measured inl vs input voltage (c in = 0) differential input voltage (v) ?1.25 ?0.75 ?0.25 inl (lsb) 1 3 24613 f10 ?1 0 2 ?2 ?3 0.25 0.75 1.25 c in = 0.1f v cc = 5v t a = 25c r s = 10k r s = 1k r s = 0k differential input voltage (v) ?1.25 ?0.75 ?0.25 inl (lsb) 1 3 24613 f11 ?1 0 2 ?2 ?3 0.25 0.75 1.25 c in = 0 v cc = 5v t a = 25c r s = 10k r s = 1k r s = 0k
ltc2461/ltc2463 17 24613fa package description dd package 12-lead plastic dfn (3mm 3mm) (reference ltc dwg # 05-08-1725 rev a) 3.00 0.10 (4 sides) note: 1. drawing is not a jedec package outline 2. drawing not to scale 3. all dimensions are in millimeters 4. dimensions of exposed pad on bottom of package do not include mold flash. mold flash, if present, shall not exceed 0.15mm on any side 5. exposed pad and tie bars shall be solder plated 6. shaded area is only a reference for pin 1 location on the top and bottom of package 0.40 0.10 bottom view?exposed pad 1.65 0.10 0.75 0.05 r = 0.115 typ 1 6 12 7 pin 1 top mark (see note 6) 0.200 ref 0.00 ? 0.05 (dd12) dfn 0106 rev a recommended solder pad pitch and dimensions apply solder mask to areas that are not soldered 0.23 0.05 0.25 0.05 2.25 ref 2.38 0.05 1.65 0.05 2.10 0.05 0.70 0.05 3.50 0.05 package outline pin 1 notch r = 0.20 or 0.25 45 chamfer 2.38 0.10 2.25 ref 0.45 bsc 0.45 bsc
ltc2461/ltc2463 18 24613fa package description ms package 12-lead plastic msop (reference ltc dwg # 05-08-1668 rev ?) msop (ms12) 1107 rev ? 0.53 0.152 (.021 .006) seating plane 0.18 (.007) 1.10 (.043) max 0.22 ? 0.38 (.009 ? .015) typ 0.86 (.034) ref 0.650 (.0256) bsc 12 11 10 9 8 7 note: 1. dimensions in millimeter/(inch) 2. drawing not to scale 3. dimension does not include mold flash, protrusions or gate burrs. mold flash, protrusions or gate burrs shall not exceed 0.152mm (.006") per side 4. dimension does not include interlead flash or protrusions. interlead flash or protrusions shall not exceed 0.152mm (.006") per side 5. lead coplanarity (bottom of leads after forming) shall be 0.102mm (.004") max 0.254 (.010) 0 ? 6 typ detail ?a? detail ?a? gauge plane 5.23 (.206) min 3.20 ? 3.45 (.126 ? .136) 0.889 0.127 (.035 .005) recommended solder pad layout 0.42 0.038 (.0165 .0015) typ 0.65 (.0256) bsc 4.039 0.102 (.159 .004) (note 3) 0.1016 0.0508 (.004 .002) 1 2 3 4 5 6 3.00 0.102 (.118 .004) (note 4) 0.406 0.076 (.016 .003) ref 4.90 0.152 (.193 .006)
ltc2461/ltc2463 19 24613fa information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no representa - tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. revision history rev date description page number a 5/11 added synchronizing the ltc2461/ltc2463 with the global address call to the applications information section 12-13
ltc2461/ltc2463 20 24613fa linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 l fax : (408) 434-0507 l www.linear.com linear technology corporation 2009 lt 0511 rev a ? printed in usa related parts part number description comments ltc1860/ltc1861 12-bit, 5v, 1-/2-channel 250ksps sar adc in msop 850a at 250ksps, 2a at 1ksps, so-8 and msop packages ltc1860l/ltc1861l 12-bit, 3v, 1-/2-channel 150ksps sar adc 450a at 150ksps, 10a at 1ksps, so-8 and msop packages ltc1864/ltc1865 16-bit, 5v, 1-/2-channel 250ksps sar adc in msop 850a at 250ksps, 2a at 1ksps, so-8 and msop packages ltc1864l/ltc1865l 16-bit, 3v, 1-/2-channel 150ksps sar adc 450a at 150ksps, 10a at 1ksps, so-8 and msop packages ltc2360 12-bit, 100ksps sar adc 3v supply, 1.5mw at 100ksps, tsot 6-pin/8-pin packages ltc2440 24-bit no latency )8 ? adc 200nv rms noise, 4khz output rate, 15ppm inl ltc2480 16-bit, differential input, no latency )8 adc, with pga, temp. sensor, spi easy-drive input current cancellation, 600nv rms noise, tiny 10-lead dfn package ltc2481 16-bit, differential input, no latency )8 adc, with pga, temp. sensor, i 2 c easy-drive input current cancellation, 600nv rms noise, tiny 10-lead dfn package ltc2482 16-bit, differential input, no latency )8 adc, spi easy-drive input current cancellation, 600nv rms noise, tiny 10-lead dfn package ltc2483 16-bit, differential input, no latency )8 adc, i 2 c easy-drive input current cancellation, 600nv rms noise, tiny 10-lead dfn package ltc2484 24-bit, differential input, no latency )8 adc, spi with temp. sensor easy-drive input current cancellation, 600nv rms noise, tiny 10-lead dfn package ltc2485 24-bit, differential input, no latency )8 adc, i 2 c with temp. sensor easy-drive input current cancellation, 600nv rms noise, tiny 10-lead dfn package ltc6241 dual, 18mhz, low noise, rail-to-rail op amp 550nv p-p noise, 125v offset max ltc2450 easy-to-use, ultra-tiny 16-bit adc, spi, 0v to 5.5v input range 2 lsb inl, 50na sleep current, tiny 2mm w 2mm dfn-6 package, 30hz output rate ltc2450-1 easy-to-use, ultra-tiny 16-bit adc, spi, 0v to 5.5v input range 2 lsb inl, 50na sleep current, tiny 2mm w 2mm dfn-6 package, 60hz output rate ltc2451 easy-to-use, ultra-tiny 16-bit adc, i 2 c, 0v to 5.5v input range 2 lsb inl, 50na sleep current, tiny 3mm w 2mm dfn-8 or tsot package, programmable 30hz/60hz output rates ltc2452 easy-to-use, ultra-tiny 16-bit differential adc, spi, 5.5v input range 2 lsb inl, 50na sleep current, tiny 3mm w 2mm dfn-8 or tsot package ltc2453 easy-to-use, ultra-tiny 16-bit differential adc, i 2 c, 5.5v input range 2 lsb inl, 50na sleep current, tiny 3mm w 2mm dfn-8 or tsot package ltc2460 16-bit, )8 spi adc with 10ppm max reference single-ended, tiny 12-lead 3mm w 3mm dfn and msop packages ltc2462 16-bit, )8 spi adc with 10ppm max reference differential input, tiny 12-lead 3mm w 3mm dfn and msop packages no latency )8 is a trademark of linear technology corporation. 0.1f v cc in + in ? 24613 ta02 10f 0.1f 7, 11, 4 8 121 0.1f 0.1f 0.1f 1k 5k 1k 10 9 6 5 sck/scl mosi/sda miso/sdo gnd 4 7 5 1f v cc v cc 8 c v cc in + refout ref ? v cc gnd 2 comp in ? ltc2463 scl sda 3 a0 0.1f 5k v cc typical application

▲Up To Search▲

Price & Availability of LTC2461IMSPBF

	To Download LTC2461IMSPBF Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .